Such an integrated circuit test system is known in which a plurality of integrated circuit devices are tested simultaneously in parallel on the electric characteristics thereof. A conventional integrated circuit test system comprises an integrated circuit tester (referred to as a circuit tester hereinafter), a test board for receiving each of integrated circuit devices under test (referred to as DUTs hereinafter) at a receiving member or a socket portion thereof, and an auto-handler for mounting and demounting the DUTs.
Information signals are exchanged between the circuit tester and the auto-handler during a test sequence for a subsequent automated classification of DUTs by the auto-handler. A plurality of DUTs are mounted to respective sockets of receiving members on the test board by respective handling members each mounted on the auto-handler. The auto-handler supplies a signal for information related to existence of DUTs (referred to as an existence information signal SDUT hereinafter) to the circuit tester through an interface cable disposed between the circuit tester and the auto-handler after mounting the DUTs on the receiving members. The existence information signal SDUT includes individual existence signals for the information whether or not each of the individual receiving members is provided with a DUT.
The circuit tester carries out electrical measurements at the signal lines of the receiving members which are provided with DUTs, on the basis of the existence information signal SDUT. After the measurements of the electric characteristics are finished, a signal for information related to the test results (referred to as a result information signal SJ hereinafter) is transferred from the circuit tester to the auto-handler through the interface cable. The result information signal SJ includes individual result signals for the information of test results of the individual DUTs.
The auto-handler then operates classification and storage of the tested DUTs on the basis of the result information signal SJ. Although there are other information to be exchanged and other several signals such as synchronizing signals in the test system, the classification and the subsequent storage are carried out, in principle, on the basis of the alternate exchange of the existence information signal SDUT and the result information signal SJ as described above.
An integrated circuit test system, in which a number of DUTs are tested simultaneously in parallel, usually employs a controller such as a GP-IB (IEEE-488) controller for transmitting the information signals between the circuit tester and the auto-handler, the GP-IB enabling transmission of many information signals simultaneously through a limited number of signal transmission lines.
With a conventional test system employing, for example, GP-IB controller, the receiving member disposed on the test board must be numberred beforehand for a correct transmission of the existence information signal SDUT and the result information signal SJ. The numberring of DUTs, e.g. DUT1 to DUTn, must be uniformed in the test system, i.e. the numberring of the handling members employed in the auto-handler must be consistent with the numberring of the corresponding DUTs employed in the circuit tester.
After DUTs are mounted on the receiving members of the test board by the auto-handler, the auto-handler supplies the circuit tester with an existence information signal. The existence information signal is exemplified in FIG. 1, which shows a three-byte existence information signal SDUT related to the test board shown in FIG. 2. FIG. 2 shows, as an example, a test board i in which DUT1, DUT2, DUT4, DUT5, DUT7 and DUT8 are actually provided on the respective receiving members among all of the 1st to 8th receiving members.
GP-IB controller usually employs 8-bit signals, the lower four bits of which represent the content of the data. Hence, transmission of the existence information signal requires 3-bite signal as shown in FIG. 1. The first byte of FIG. 1 declares that this signal is related to an existence information signal SDUT, the second and the third bytes represent the actual existence information as to the individual eight receiving members.
When the circuit tester receives the existence information signal SDUT of FIG. 1, the circuit tester understands the content of the existence information based on the received signal and the predetermined format of the signal transmission, then starts electric measurements of the individual DUTs which are informed as existing on the receiving members in the existence information signal SDUT.
After the electric measurement of each of the DUTs then present on the test board is completed, the circuit tester supplies the auto-handler with a result information signal SJ as shown in FIG. 3 through the interface cable. The result information signal SJ includes nine bytes, first of which declares that the signal is a result information signal SJ and the rest of which show the individual test results thereof. In this example, since each of the individual test result signals SJa to SJh is constituted by a 4-bit signal, the individual result information can be categorized in sixteen classifications.
When the auto-handler receives the result information signal SJ of FIG. 3 from the circuit tester, the auto-handler understands the test results of the individual DUTs represented by the individual test result signals SJa to SJh on the basis of the received signal and the predetermined format, then starts for classification and storage operation with its handling members.
Upon a parallel measurement of a plurality of DUTs in a conventional test system as described above, the numberring of DUTs on the test board by the circuit tester must be consistent with the numberring of the corresponding handling members by the auto-handler for a correct transmission of the information signals. An error, however, sometimes occurs in the numberring between the circuit tester and the auto-handler, due to an inconsistency of the numberring format between the test board and the auto-handler or due to a wrong connections between the test board and the circuit tester. Such an error would lead to a problem of a miss classification resulting in, for example, a shipment of a defective integrated circuit device.